1. Board overview
This card is based on the IDT TSI721 bridge chip, which is used to realize the conversion of Serial RapidIO (S-RIO) Gen2.1 to PCI Express (PCIE) Gen2.1 protocol, and extends the RapidIO-based peer-to-peer network multi-processor cluster to the x86 processor environment, which can realize high-speed data transfer between the RapidIO-based peer-to-peer network multi-processor cluster and the x86-based processor environment.
This card can provide 1 high-speed QSFP+ connector optical fiber S-RIO transceiver interface.
System block diagram
2. Functional and technical indicators
Features of the PCIe side:
- Supports the PCIe 2.1 protocol standard
- The rate of the channel can be configured. The rate of the channel: 5/2.5Gbaud Link speed
- Number of transmission channels：4 x Lanes
Features of the S-RIO side:
- Supports the S-RIO 2.1 standard
- The speed rate of the channel can be configured：5/3.125/2.5/1.25Gbaud Link speed
- Flexible Physical Transmission Interface: 1 channel 4x Link Width QFSP+ fiber optic transceiver interface
- Supports Lanes ReversalFeatures of the board:
- Supports the IEEE 1149.1/1149.6 JTAG debug interface
- Debug interface that supports the I2C standard
- Flexible configuration: The DIP switch is configured with TSI721 working mode
- Power supply: PCIE power supply or standard ATX 12V power supply interface
- 1 reset button for system reset
- Provide a Window driver
- The demo program in the window is provided
- All components support commercial and industrial grades
3. the field of application
- Sonar signal processing platform
- Software Defined Radio Processing Platform
Image signal processing platform
4.Product Specifications
| Parameters/Functions |
Detailed Description/Specifications |
| Core chips |
JXW721 bridge chip, support bidirectional protocol conversion and high-speed data transmission |
| PCIe capability |
Gen2.1, support x4/x2/x1 mode, rate 2.5Gbps/5Gbps, adaptive motherboard. |
| SRIO function |
Gen2.2，Supports x4/x2/x1 mode, rate 1.25Gbps/2.5Gbps/3.125Gbps/5Gbps。
API function to set X mode and speed |
| SRIO interface |
QSFP+ optical interface (1 SRIO port, 1 PCIe port)
Supports hot-swappable and IEEE 1149.1/1149.6 test standards. |
| Board transfer capability |
The board supports front-end AD to fiber and image to fiber data server access.
The maximum total bandwidth is 16 Gbit/s
It supports 4 inputs for high-definition 1080P images and 2 channels for 500Msps@ 16bit AD |
| Power supply mode |
Power supply mode: PCIe gold finger direct power supply. |
| Power consumption of the entire board |
4.6W (typical). |
| Environmental adaptability |
Temperature: -40°C ~ 85°C.
Humidity: 5%~85%RH. |
| Size range (L×W) |
162mm(L) x 68.9(W, including gold finger) |
| Mechanical compatibility |
Half-height and half-length PCIe standard design, suitable for general-purpose chassis and industrial equipment. |
| weight |
51.5g |
5.Adaptation platform
The TSI721 (JXW721) PCIe to RapidIO high-speed data transfer card is an adapter bridge board, which is suitable for different motherboards and operating systems.
The software and hardware environment requirements related to the specific system are as follows:
1. There are no special requirements for CPU processor architecture and model, and Loongson, ARM, and x86 architectures are recommended
2. Linux is recommended for the operating system, kernel version 3.10.0 or later, and centos 7.4/8.2 is recommended for distribution version
3. Therecommended driver is JXW721 official driver
4. The driver installation environment requires that the Linux system does not have a built-in RAPIDIO driver, and the method is as follows:
Execute the following commands:
grep RAPIDIO /boot/config-$(uname -r)
Check if CONFIG_RAPIDIO is configured:
If you have already configured it, you will need to re-customize the kernel, remove the CONFIG_RAPIDIO configuration options in .config and recompile it to use the newly compiled kernel (if you are using the recommended Linux distribution, you can ignore this step).
List of software and hardware adaptation platforms:
Table 4.1 List of processors and system versions that have passed SDK software tests (including but not limited to this list)
| processor |
System version |
Kernel version |
Motherboard model |
| X86 |
centos-7.4.1708 |
3.10.0 |
|
| ubuntu-16.04 |
4.15.0-112-generic |
|
| ubuntu-18.04 |
5.4.0 |
|
| ubuntu-22.04 |
6.5.8 |
ASUS 8250plus |
| fedora-35 |
5.16.16 |
|
| FT-2000/4 |
kylin-v10 |
4.19.0 and 4.4.131 |
|
| Tianmai 3 |
ACoreOSMP V1.0.6.02 |
|
| Loongson-3A4000 |
UnionTech |
4.19.0 and 4.19.190 |
|
| ZYNQ 7035（ARMv7 Processor rev 0 (v7l)） |
Embedded Linux system |
4.14.0-xilinx-v2018.2 |
|
5.Function description
In order to facilitate users to save development time, we have encapsulated a wealth of API functions, and the following lists some commonly used functions and their descriptions
| serial number |
API functions |
Feature description |
Key parameters |
| 1 |
rio_mport_open() |
This function implements the opening of the rio_mport character device interface, wherein if N bridge devices are mounted on the PCIE interface, the mport_id number 0~N-1 is used to implement access to the different bridge devices |
Device parameters
Operational permission flags |
| 2 |
rio_cm_open() |
This function opens the rio_cm character device interface without passing in parameters |
not |
| 3 |
rio_dma_write() |
This function initiates a write operation to the peer through DMA to convert the cache data of the user-space application to the peer device cache through the bridging protocol according to the user-configured mode and parameters |
The ID of the destination SRIO device
SRIO bus start address
The length of the data to be migrated |
| 4 |
rio_dma_read() |
This function initiates a read operation from DMA to the cache applied for in user space, that is, the data in the peer cache is converted and read to the PCIE cache of the local device through the bridging protocol according to the mode and parameters configured by the user. |
The ID of the destination SRIO device
SRIO bus start address
The length of the data to be migrated |
| 5 |
rio_wait_async() |
This function is used to wait for the DMA asynchronous transfer to end |
DMA Transport ID Flag |
| 6 |
rio_ibwin_map () |
This function maps the SRIO address space to the local kernel data cache space through the mapping engine, and converts the SRIO bus address of the inbound SRIO read and write request into the PCIE data cache configuration |
SRIO base address |
| 7 |
rio_ibwin_free () |
This function frees the buffer for the mapping of SRIO space to local kernel space data |
The physical address of the memory space is reserved |
| 8 |
rio_lcfg_read () |
This function is used for local mport device register read access through the PCIE interface. |
The number of bytes accessed by the register |
| 9 |
rio_lcfg_write () |
This function is used for local mport device register write access through the PCIE interface |
The register address is offset by the value that is written to the access |
| 10 |
rio_socket_socket () |
This function is used to create SRIO socket struct pointer variables based on a given mailbox |
SRIO socket struct pointer parameters |
| 11 |
rio_socket_listen () |
This function is used on the server side to enable the server to listen for connection requests for a specific virtual channel |
SRIO socket struct parameters |
| 12 |
rio_socket_accept () |
This function is used on the server to accept connection requests initiated by clients. If the timeout parameter is not 0, the function will block execution; If the timeout parameter is 0, the execution is non-blocking |
SRIO socket struct parameters |
6. Board Accessories
table 5.1 Board accessories
| serial number |
The name of the accessory |
quantity |
| 1 |
Optical Transceiver (QSFP+) |
1 |
| 2 |
Fiber Optic (MPO-MPO) |
1 |
| 3 |
Main chip heatsink |
1 |
| 4 |
PCIe Bezel (Half-Height, Full-Height) |
1 |
7 Board Applications
7.1 In defense applications:
The JXW721 supports processors with PCIe interfaces for RapidIO network interconnection. Using JXW721 in combination with Wellcore's RapidIO Gen2 switch chip, payload processor cards with various processor models can work with the RapidIO Gen2 interconnect system.
7.2 In video and image applications:
System designers need a large number of DSPs or FPGAs to perform encoding/decoding/transcoding operations, or to perform FFT (Fast Fourier Transform) on large data arrays. The RapidIO protocol is best suited for this DSP/FPGA cluster requirement. In such applications, designers need to build a data path between a PCIe network and a RapidIO network, DSP, or FPGA cluster. The JXW721 is very suitable for this application scenario.
7.3 Wireless Applications:
In wireless base stations, the interconnection technology employed by the baseband processing cards (LTE, WiMAX, WCDMA, and TD-SCDMA) is RapidIO. A cluster of DSPs, processors, and FPGAs is connected over a RapidIO network for data processing.
The JXW72 provides wireless device manufacturers with an additional design option to use processors with superior MIPs in RapidIO-based baseband cards. RapidIO is an interconnect bus between devices and is used for backplane interconnects. The processor is based on RapidIO's messaging mechanism and can work with other RapidIO devices on the baseband card.
