1. Board overview
This card realizes 1-channel 1GspsAD data acquisition and transmits it to the server through PCIe to realize data collection, storage and calculation. Front-end AD acquisition supports DC AC coupling inputs.
The AD capture PCIe card hardware is based on the Xilinx FPGA XCKU060 as the core, combined with ADI's AD chip AD9680 to design a general-purpose PCIe capture card, and its schematic block diagram is as follows:
2. Hardware specifications
● XCKU060-2FFVA1156I;
● FPGA adopts BPI loading mode;
● External 1 AD9680 chip, support 1Gsps sampling, support front-end amplification, ± 3V input range, 2 AD interfaces are SMA connectors;
● The clock chip uses AD9528, supports 10MHz internal reference, and external reference input, and supports OSC 100MHz
● Support dual-channel DDR4, 64bit per group, 4GB capacity.
● Reserved JTAG and 16 extended IOs, LVTTL 3.3V level;
● Support 4 LED indicators for status display.
● Support the use of EEPROM to store data;
●The total size of the board is controlled within 10cmX10cm.
● Support power +12V input, estimated power consumption within 40W.
● The board cold plate has a fanless structure, which is installed in the cavity of Party A's equipment, and the shell provides screw holes and cooling conduction structure.
2.1 ADC Functions and Performance
A. Single-channel sampling: 1G sampling rate (14 bit AD), the maximum sampling period is 50,000 times in 1s (the length of each acquisition is 10us), that is, the maximum data rate is 500MBps.
Note: The length of each acquisition (i.e., the trigger length) can be set, and the rate should not exceed 500MBps according to the number of samples and the length of time.
B. THE SAMPLING FREQUENCY CAN BE SET (SUCH AS 500M, 250M, 125M SAMPLING RATE);
C. Voltage input range: not less than ±3V input range;
2.2 Interface Description
● In the SMA interface of the original board card
● Clock interface: external CLK, can be removed, no need (the card implements its own sampling clock to provide).
● RES interface: can be removed, no need required
Two modes:
A. Internal trigger: usually used for testing, self-triggering sampling, up to 24 times of sampling in 1s (trigger time can be set);
B. External trigger: sampling through the E-TRIG signal of the SMA interface (please refer to the PCIe9802S manual for details)
C. About I-TRIG signal: The output signal of the board, when the external trigger, the E-TRRIG can be directly connected to the I-TRIG, and when the internal trigger is triggered, the I-TRIG output internal trigger pulse.
3. Software development content
3.1 Introduction to Software Development Tools
| name |
version |
remark |
| FPGA software development |
Vivado2018.3 Verilog Language |
|
| PCIE driver development |
XDMA frame，WinDriver |
|
| PC software development |
Windows10 64bit Qt5 |
|
3.2 Basic content of software development
(1) Software single-channel sampling: 1G sampling rate (14 bit AD), the maximum sampling period is 1s, 50,000 times of acquisition (each acquisition length is 10us), that is, the data rate is up to 500Mbyte, the data is cached into DDR, and then uploaded to the PC through PCIe.
(2) The length of each acquisition (i.e., the trigger length) can be set, and the sampling time interval (period) can be set, and the rate does not exceed 500MBps according to the number of samples and the length of time.
(3) The sampling frequency can be set (such as 500M, 250M, 125M sampling rate); AD has been working at 1Gsps sampling, and the sampling frequency is achieved by decimation in the FPGA, with sampling rates of 500M, 250M, and 125M.
(4) The FPGA software uses the Xilinx XDMA PCIe software framework to realize AD caching and uploading. Implements DMA transmission, interrupt, IO register configuration.
(5) The PC host computer software can realize the storage of data, the maximum file is not more than 1GByte, the file content is 1024 bytes, the sampling frequency is described, the acquisition length, the collection time interval, and the current time of the acquisition computer (year, month, day, hour, minute, second, millisecond); The software interface realizes local playback of AD data, sine wave display and binary value display.
3.3 Overall Workflow
(1) The user sets the acquisition parameters, sampling channel, sampling length, sampling method and other information through the host computer, and sets the AD acquisition parameters through PCIE;
(2) The AD acquisition device receives the command and starts to collect AD data according to the corresponding parameters;
(3) The AD acquisition device obtains the AD data and imports it into the host computer through PCIE;
(4) The host computer obtains the data and selects to store it on the hard disk or display. |
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