534-Binocular vision development suite based on MPSOC XCZU3EG

534-Binocular vision development suite based on MPSOC XCZU3EG

Name: 534-Binocular vision development suite based on MPSOC XCZU3EG
Brand: Orihard
SKU: 534
Availability: InStock
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Item No.: 534

This platform mainly for deeper study of senior undergraduate, master's students major in electronics, computer, automation, electronics, communications and other major, through the complete binocular vision hardware platform (including a camera module, M

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Description

534-Binocular vision development suite based on MPSOC XCZU3EG

(1) Overview of binocular vision platform
This platform mainly for deeper study of senior undergraduate, master's students major in electronics, computer, automation, electronics, communications and other major, through the complete binocular vision hardware platform (including a camera module, MPSOC core board, interface board), understand the whole image transmission, processing hardware system, through the whole of the binocular vision software (including PL end firmware program, ARM end naked running program, PC network) understanding of video synchronous transmission, AXI bus interrupts, VDMA LWIP protocol stack, video transmission, network video transmission and video display, etc., In-depth understanding of the underlying data flow transmission process, continuous flow interrupt, memory management mechanism, network TCP/UDP IP mechanism.
Through the learning of this suite, students can lay a good foundation for the integration of embedded underlying hardware and software, and make full preparations for future work in image processing, artificial intelligence, chip design, cloud intelligent video and other fields.
This platform can also provide new employees with a deep understanding of the whole process of video collection, transmission and processing, as well as the basic idea of binocular vision access, and quickly experience the idea and practice process of combining software and hardware through learning hardware and underlying code.
(2) Binocular vision software content
Thick software code content and detailed explanation brings far more value than the development board
Binocular vision software introduces the video transmission system in the process of image transmission through an engineering case, binocular video access, DP display, VDMA video transmission by AXI bus, ARM LWIP protocol network transmission, and PC network image access and display through a complete software code depth. The code module learning and introduction are as follows:

serial number	program name	Program content
1	Binocular video PL terminal image access	Through THE SENSOR setting of PL, access to binocular visual row field and data information, experience the concept of row field resolution, and understand the characteristics of binocular synchronization.
2	Single-channel CMOS image Sensor to DP display experiment	Learn the data characteristics of video display, RGB signal characteristics, and the corresponding relationship between data and display through PL terminal code.
3	AXI bus for VDMA image transmission	Through the interaction between PL side program and PS side, understand the DMA transfer mechanism of video frame transmission, DDR cache, interrupt interactive relationship, continuous image storage and data flow mechanism of algorithm application.
4	ARM's LWIP network transmission experiment	C program code based on naked running how to completely present UDP/TCP, IP protocol data transceiver, network packet mechanism and transmission mechanism, image network transmission data packet protocol.
5	Experiment of PC transmission in double channel video network	QT program of upper computer, how to receive image data on the network, realize the analysis of network protocol, data flow caching mechanism, display continuous image display and continuous receive packet interaction.

(3) Hardware introduction of binocular vision platform
The binocular vision platform suite, based on the most advanced MPSOC chips, is designed through the core board + expansion board mode, with high-speed inter-board connectors connecting the core board and expansion board. The whole structure from the camera to the main processor and the interface circuit is built. The overall framework is as follows:

This MPSoCs development platform adopts the mode of core board and extension board, which facilitates the secondary development and utilization of the core board.
2.1 The core board
The core tablet USES the XILINX Zynq UltraScale+ CG chip ZU3EG solution, which USES Processing System(PS)+Programmable Logic(PL) technology to integrate dual-core ARM Cortex-A53 and FPGA Programmable Logic Logic on a single chip. In addition, the PS terminal on the core board is equipped with four 2GB high-speed DDR4 SDRAM chips, a 8GB eMMC memory chip and two 512Mb QSPI FLASH chips. The PL side of the core board has a 512MB DDR4 SDRAM chip.
2.2 The motherboard
In the motherboard design, we extend rich peripheral interfaces for users, such as a FMC LPC interface, a SATA M.2 interface, 1 DP interface, a USB3.0 interface, 1 gigabit Ethernet interface, a UART serial port interface, a SD card interface, two 40-pin extension interfaces, two CAN bus interfaces, two RS485 interfaces and so on. ZYNQ is a "professional" development platform that meets the needs of users for high-speed data exchange, data storage, video transmission processing, deep learning, artificial intelligence, and industrial control. For high speed data transmission and exchange, it provides the possibility of early validation and late application of data processing. It is believed that such a product is very suitable for students and engineers engaged in MPSoCs development.

Core plate check motherboard structure diagram:

Through this diagram, we can see the interfaces and functions that our development platform can contain.
2.3 OV5642 binocular camera module
OV5642 camera module adopts us OmniVision(Howe)CMOS chip image sensor OV5640, which supports two independent or simultaneous display functions. CMOS OV5640 chip supports DVP and MIPI interface, and image transmission is realized through DVP interface and FPGA connection on OV5642 module.
Parameter description of OV5642 camera module
The detailed parameters of OV5642 module are as follows:

Interface: 40-pin master seat, 2-way camera adopts a separate DVP interface
Spacing: the spacing between 2-way cameras is 40mm;
Pixel: hardware pixel 500W;
Photosensitive chip: two OV5640;
Sensor size: 1/4;
Module content: including OV5640 power circuit and clock;
Function support: manual focus, Automatic exposure control (AEC), automatic white balance (AWB);
Image formats: RAW RGB, RGB565/555/444,CCIR656, YUV422/420, YCbCr422 and compression;
Captured images: QSXGA(2592x1944), 1080P, 1280x960, VGA(640x480), QVGA(320x240);
Operating temperature: -30~70℃, stable operating temperature is 0~50℃

Real picture of OV5642 module: