1. Overview of the board
4-channel QSFP28 fiber PCIeX16 transceiver card based on XCVU9P. The board complies with PCIe 3.0 standards and contains one XCVU9P-2FLGA2014I and four groups of 64-bit/8GB DDR4. 4 QSFP28 4X optical fibers, each optical fiber supports 4X25Gbps, bidirectional; Supports 36 I/OS. The operating temperature range of the board is 0 to 60℃. The design and processing of the board include heat dissipation device, which supports the server air cooling heat dissipation. The software includes interface test software to support the application development of Party A.
2. hardware composition
2.1 The hardware diagram of board logic is shown in the figure:
2.2 Function Indicators
● The main chip uses XCVU9P-2FLGA2014I industrial-grade chip. Or XCVU13P-2FHGA2014I
● The board complies with PCIe 3.0 specifications, adopts x16 mode hardware design, theoretical bandwidth up to 64Gbps, supports PCIex8 mode use, and the test rate can reach 5000MByte/s under Linux system.
● Support 4 QSFP+ 4X optical fibers, each optical fiber supports 4X25Gbps, bidirectional;
● Support 36 IO, level is 1.8V, bidirectional can be set; 8 3.3V IO, direction fixed.
● Four LED indicators, four user dip switches.
● Four sets of onboard 64-bit DDR4, each with a total capacity of 8GB, can work stably at 1200MHz(2400MT/s).
● 2 SPI x4 NorFlash for program loading and 1 I2C E2PROM for program encryption.
● JTAG debugging port is located on the upper edge of the board, which is convenient for debugging after the board is inserted into the chassis.
● Board structure Full height PCIe standard card, the length is controlled within 2/3 of the full length, plus heat dissipation board, chassis air cooling heat dissipation, provide front baffle.
● Board operating temperature range 0 to +60℃.
● Board power supply 12V(±10%), PCIe slots can be supplied separately, or external power supply can be used separately; Typical power consumption 100W.
3. Software content
The board development software mainly completes the hardware interface test and program loading. Mainly for FPGA configuration program loading test, parameter storage Flash read and write test, DDR4 read and write test, optical fiber transceiver data test, GPIO test. The software used in this test manual includes:
● FPGA software development tool Vivado2021.2, Verilog language development; PCIe runs on a windows or Linux PC.
● Interface software includes the following:
● Board hardware testing;
● Flash loading test code;
● DDR4 test code, four groups work at the same time, work alone;
● Fiber ibert loop test;
● PCIe3.0 x16 mode XDMA test, including FPGA code, driven by PC in Linux system;
● Other GPIO test code.
The above program provides test cases, test methods, test reports and instruction manuals
(Note: Party A shall provide the server for software test and acceptance to ensure the compatibility of subsequent use)
