1. Product Overview
The board is a high-resolution, high-sampling-rate ADC FMC daughter board. It provides two 12-bit 3.2GS/s A/D channels or one 6.4GS/s A/D channel, and the full-power analog input bandwidth can reach 6GHz. This design is based on TI's ADC12DJ3200 analog-to-digital conversion chip. The board supports trigger output/trigger input; internal reference clock and external reference clock modes. The reference clock can be used to synchronize multiple boards.
The electrical and mechanical design of the board is based on the FMC standard (ANSI/VITA 57.1) and is connected to the FPGA carrier board via a high-density connector (HPC). The front panel I/O is equipped with SSMC coaxial connectors. The board is designed with air cooling or conduction cooling .
2. Main specifications:
● 2 channels 12bit 3.2GS/s AD or 1 channel 6.4GS/s AD
● 6GHz analog bandwidth
● Applicable to the third Nyquist zone
● Compatible with VITA57.1 specification
● Air cooling or conduction cooling
● AC coupled input
● Internal clock, external clock and external reference clock
● HPC High Pin Count Connector
● 6 SSMC front panel connectors
● 2kbit EEPROM (M24C02-WDW) can be connected to the motherboard via I2C bus
3. Customer Support
● Fast delivery
● Good maintainability
Easy to integrate
● High speed and high precision selection
● Other support:
● Provide Verilog bit files
● Open source C/C++ reference examples
● JESD204B Core, including BSP
